The present invention relates to a phase comparator for detecting the difference in phase between two signals with high precision and, more particularly, to a sample-and-hold-type digital phase comparator.
A digital mobile communication system is now being developed as a next generation mobile communication system which will take the place of conventional analogue mobile communication systems. A frequency synthesizer for use in radio equipment for digital mobile communication is adapted to be capable of switching its oscillation frequency, for example, at intervals of 25 kHz around 800 MHz for switching the channel. The frequency switching time needs to be reduced far shorter than in the case of the analogue system. This calls for the development of a frequency synthesizer capable of high-speed switching of frequency and necessitates further reduction of its size and power dissipation as well.
The frequency synthesizer for mobile communications is an oscillator utilizing phase locked loop (PLL) technology. The frequency switching time of such a frequency synthesizer could be effectively reduced by increasing the sensitivity of a phase comparator that is used in the phase locked loop. On the other hand, it is effective in the miniaturization of the synthesizer to form the phase comparator by a digital circuit.
In FIG. 1 there is shown, as a prior art example of the comparator formed by a digital circuit, the principal part of a sample-and-hold-type phase comparator disclosed in Utsui et al, "DIFFERENTIAL DETECTOR USING DIGITAL IC's," IEICE Japan Technical Report CS82-122. This phase comparator outputs, as an m-bit binary number, a phase difference .DELTA..phi. between a reference signal S.sub.R generated by a reference signal generator 13 and an input signal under measurement, Sx, provided to an input terminal 10. The reference signal generator 13 is made up of a pulse generator 13A and a modulus counter 13B. The modulus counter 13B counts clock pulses PCK (FIG. 2, Row B) from the pulse generator 13A to modulus M which is an integer, and repeatedly outputs a series of count values Cm incremented one by one from O to M. The reference signal level Cm, which is the count value of the counter 13B, takes a staircase-like saw-tooth waveform as shown in FIG. 2, Row A which shows the case of M=3. Thus, the count value Cm corresponds to the phase of the reference signal S.sub.R.
The M+1 count values of the modulus counter 13B from O to M are each assigned or allotted to one of M+1 equally-displaced phase values 0 to 2.pi. rad of the phase .phi..sub.R of the reference signal S.sub.R (which phase .phi..sub.R will hereinafter be referred to as a reference phase). The count value Cm of the counter 13B corresponding to the reference phase .phi..sub.R is sampled by a latch circuit 14 through use of a trigger signal Tr synchronized with the input signal Sx and the sampled value is held as a value corresponding to the phase difference .DELTA..phi. between the input signal Sx and the reference signal S.sub.R. In the example of FIG. 2, a trigger generator 17 generates the trigger signal Tr of Row C (a negative pulse in this example) by the positive edge of the input signal Sx of Row D. By the positive edge of the trigger signal Tr the latch circuit 14 is driven to fetch thereinto the count value Cm of the counter 13B at that time point. The output value Cm of the latch circuit 14 is a binary m-bit digital signal corresponding to the phase difference .DELTA..phi.between the reference signal S.sub.R and the input signal Sx, and the binary m-bit digital signal will hereinafter be identified by the same symbol .DELTA..phi. as that of the above-said phase difference.
In such a sample-and-hold-type digital phase comparator as described above, the magnitude of a minimum unit phase or phase accuracy (i.e. a quantization error of phase or quantization step of phase) .phi..sub.Q of the reference phase .phi..sub.R depends on the modulus M which is the maximum count value of the counter 13B, and it can be expressed as follows: EQU .phi..sub.Q =2.pi./(M+1) (1)
Here, the reference phase .phi..sub.R varies with the count value Cm of the modulus counter 13B as expressed as follows: EQU .phi..sub.R =.phi..sub.Q Cm EQU Cm=0, 1, 2, . . . , M, 0, 1, 2, . . . , M, 0, 1, 2, . . . (2)
To increase the sensitivity of such a digital phase comparator, the reduction of the quantization step .phi..sub.Q is needed, which is, however, difficult for the reasons given below. As indicated by Eq. (1), the quantization step .phi..sub.Q is dependent on the maximum count value or modulus M of the modulus counter 13B. For instance, a counter of m=2 bits counts from "0" to "3," and in this instance, the quantization step .phi..sub.Q is 2.pi./4 rad. Since the relationship between the number of bits, m, and modulus M of the counter 13B is M=2.sup.m -1, Eq. (1) becomes as follows: EQU .phi..sub.Q =2.pi./2.sup.m ( 3)
Hence, the quantization step .phi..sub.Q could be reduced by increasing the number of bits, m, of the modulus counter 13B. On the other hand, the frequency f.sub.CK of the clock pulse PCK from the pulse generator 13A can be expressed as follows: EQU f.sub.CK =f.sub.R 2.sup.m ( 4)
where f.sub.R is the repetition frequency of the count value Cm of the counter 13B from "0" to "M" (i.e. the frequency of the reference signal S.sub.R). As will be seen from Eq. (4), the clock frequency f.sub.CK drastically increases with an increase in the number of bits m. To realize such a very small quantization step .phi..sub.Q, it is necessary that the clock frequency f.sub.CK be remarkably higher than the frequency f.sub.R of the reference signal S.sub.R. For example, in the case of obtaining a quantization step .phi..sub.Q of 2.pi./2.sup.16 (=96 .mu.rad) when the reference frequency f.sub.R is 25 kHz, the pulse generator 13A needs to generate the clock pulse PCK at a frequency of about 1.6 GHz.
Thus, the conventional phase comparator requires a very high clock frequency f.sub.CK to obtain a very small quantization step. It is necessary, therefore, to employ, as the modulus counter 13B, a high-speed counter which operates at high frequencies. Since power dissipation of counters designed for high-speed operation is usually large, the reduction of the quantization step in the conventional phase comparator to improve its sensitivity is accompanied by the defect of its increased power dissipation.